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Features and Benefits
Leading Edge Performance
* * * 215 MHz System Performance (Military Temperature) 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) 240 MHz Internal Performance (Military Temperature) * * * * * * * * * * * Actel Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft Cold-Sparing Capability Individual Output Slew Rate Control QML Certified Devices 100% Military Temperature Tested (-55C to +125C) 33 MHz PCI Compliant CPLD and FPGA Integration Single-Chip Solution Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, and TTL Configurable Weak Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up Up to 100% Resource Utilization and 100% Pin Locking 2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with 5 V Input Tolerance and 5 V Drive Strength Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) A54SX32A 32,000 48,000 2,880 1,800 1,080 1,980 228 3 0 Yes Yes 5.3 ns 0 ns Std, -1 84, 208, 256 A54SX72A 72,000 108,000 6,036 4,024 2,012 4,024 213 3 4 Yes Yes 6.7 ns 0 ns Std, -1 208, 256
Specifications
* * * * 48,000 to 108,000 Available System Gates Up to 228 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.25/0.22 CMOS Process Technology
Features
* * * * Hot-Swap Compliant I/Os Power-Up/Down Friendly (no sequencing required for supply voltages) Class B Level Devices Three Standard Hermetic Package Options
* * * * *
Product Profile
Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Register Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary-Scan Testing 3.3 V / 5 V PCI Clock-to-Out Input Set-Up (External) Speed Grades Package (by Pin Count) CQFP
N o ve m b e r 2 0 0 6 (c) 2006 Actel Corporation
i See the Actel website for the latest version of the datasheet.
HiRel SX-A Family FPGAs
Ordering Information
A54SX32A - 1 CQ 208 M Application (Ambient Temperature Range) M = Military (-55 to +125C) B = MIL-STD-883 Class B Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard Part Number A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates
Figure 1 * HiRel SX-A Family Ordering Information
Ceramic Device Resources
User I/Os (including clock buffers) Device A54SX32A A54SX72A CQFP 84-Pin 62 - CQFP 208-Pin 174 171 CQFP 256-Pin 228 213
Note: Package Definitions: CQFP = Ceramic Quad Flat Pack
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Actel MIL-STD-883 Product Flow
Step 1. 2. 3. 4. Internal Visual Temperature Cycling Constant Acceleration Seal a. Fine b. Gross Visual Inspection Pre-Burn-In Electrical Parameters Burn-In Test Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable Final Electrical Test a. Static Tests (1) 25C (Subgroup 1, Table I) (2) -55C and +125C (Subgroups 2 and 3, Table I) b. Functional Tests (1) 25C (Subgroup 7, Table I) (2) -55C and +125C (Subgroups 8A and 8B, Table I) c. Switching Tests at 25C (Subgroup 9, Table I) 11. External Visual Screen 2010, Test Condition B 1010, Test Condition C 2001, Test Condition D, Y1, Orientation Only 1014 100% 100% 2009 In accordance with applicable Actel device specification 1015, Condition D, 160 hours @ 125C or 80 hours @ 150C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 100% 5005 5005 100% 5005 5005 5005 2009 100% 100% 100% 100% 100% 100% All Lots 883 Method 883 - Class B Requirement 100% 100% 100%
5. 6. 7. 8. 9. 10.
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Table of Contents
General Description
QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 HiRel SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Detailed Specifications
2.5 V/3.3 V/5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 5 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 3.3 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 HiRel SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Package Pin Assignments
84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
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General Description
The HiRel versions of Actel SX-A family FPGAs offer advantages for commercial applications and all types of military and high reliability equipment. The HiRel versions are fully pin compatible, allowing designs to migrate across different applications that do not have radiation requirements. Additionally, the HiRel devices can be used as a lower cost prototyping tool for RadTolerant (RT) designs. This datasheet discusses HiRel SX-A products. Refer to the Actel website for more information concerning RadTolerant products. The programmable architecture of these devices offers high performance, design flexibility, and fast and inexpensive prototyping, all without the expense of test vectors, NRE charges, long lead times, and schedule and cost penalties for design modifications that are often required by ASIC devices. Many suppliers of microelectronics components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for quality, reliable, and cost-effective logistics support throughout the life cycles of QML products.
HiRel SX-A Family Architecture
The HiRel SX-A family architecture was designed to satisfy next-generation performance and integration requirements for production volume designs in a broad range of applications.
Programmable Interconnect Element
The HiRel SX-A family incorporates either three (in HiRel A54SX32A) or four (in HiRel A54SX72A) layers of metal interconnect and provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers (Figure 1-1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs) and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules.
QML Certification
Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is an example of the Actel commitment to supplying the highest quality products for all types of high reliability, military, and space applications.
Routing Tracks
Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Metal 4
Metal 3
Tungsten Plug Via Metal 2
Metal 1 Tungsten Plug Contact Silicon Substrate
Note: HiRel A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. HiRel A54SX32A has three layers of metal with antifuse between Metal 2 and Metal 3. Figure 1-1 * HiRel SX-A Family Interconnect Elements
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Interconnection between these logic modules is achieved using Actel patented metal-to-metal programmable antifuse interconnect elements, which are embedded in the top two layers. The antifuses are normally open circuit and, when programmed, form a permanent lowimpedance connection. The extremely small size of these interconnect elements gives the HiRel SX-A family abundant routing resources and provides excellent protection against design theft. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. Additionally, since HiRel SX-A is a nonvolatile single-chip solution, there is no configuration bitstream to intercept. The HiRel SX-A interconnect elements (the antifuses and metal tracks) also have lower capacitance and lower resistance than those of any other device of similar capacity, resulting in the fastest signal propagation in the industry for the radiation tolerance offered.
This provides additional flexibility while allowing the mapping of synthesized functions into the HiRel SX-A FPGA. The clock source for the R-cell can be chosen from the hardwired clock, the routed clocks, or internal logic. The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-3). Inclusion of the DB input and its associated inverter function increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the HiRel SX-A architecture. An example of the improved flexibility enabled by the inversion capability is the ability to implement a three-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit paritytree functions with 1.9 ns of propagation delay. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time.
D0
Logic Module Design
The HiRel SX-A family architecture is described as a "seaof-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel HiRel SX-A devices provide two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell (Figure 1-2) contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals. The R-cell registers feature programmable clock polarity selectable on a register-by-register basis.
D1 Y D2 D3 Sa DB A0
Figure 1-3 * C-Cell
Sb
B0
A1
B1
Routed Data Input S1 S0 PSETB Direct Connect Input
Chip Architecture
The HiRel SX-A family chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications.
Q Y
D
Module Organization
Actel has arranged all C-cell and R-cell logic modules into horizontal banks called clusters. There are two type of clusters: Type 1 clusters contain two C-cells and one R-cell, and Type 2 clusters contain one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 1-4 on page 1-3). A Type 1 SuperCluster is a two-wide grouping of Type 1 clusters. A
HCLK CLKA, CLKB, Internal Logic CKS CKP CLRB
Figure 1-2 *
R-Cell
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Type 2 SuperCluster is a two-wide group containing one Type 1 cluster and one Type 2 cluster. HiRel SX-A devices feature more Type 1 SuperCluster modules than Type 2 SuperCluster modules because designers typically require significantly more combinatorial logic than flip-flops.
hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a single SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum pin-to-pin propagation time of 0.3 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. The Actel segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays.
Routing Resources
Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 on page 1-4 and Figure 1-6 on page 1-4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a
R-Cell
C-Cell
Routed Data Input S1 S0 PSETB Direct Connect Input
D0 D1 Y D2 D Q Y D3 Sa Sb
HCLK CLKA, CLKB, Internal Logic CKS CKP CLRB DB A0 B0 A1 B1
Cluster 1
Cluster 2
Cluster 2
Cluster 1
Type 1 SuperCluster
Figure 1-4 * Cluster Organization
Type 2 SuperCluster
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Direct Connect * No Antifuses * 0.1 ns Routing Delay
Fast Connect * One Antifuse * 0.4 ns Routing Delay
Routing Segments * Typically Two Antifuses * Max. Five Antifuses
Type 1 SuperClusters
Figure 1-5 * DirectConnect and FastConnect for Type 1 SuperClusters
Direct Connect * No Antifuses * 0.1 ns Routing Delay
Fast Connect * One Antifuse * 0.3 ns Routing Delay
Routing Segments * Typically Two Antifuses * Max. Five Antifuses
Type 2 SuperClusters
Figure 1-6 * DirectConnect and FastConnect for Type 2 SuperClusters
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Clock Resources
The Actel high-drive routing structure provides up to three clock networks (Table 1-1). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinatorial logic. This results in a fast propagation path for the clock signal, enabling the 5.3 ns clock-to-out (pad-to-pad) performance of the HiRel SX-A devices. The hardwired clock is tuned to provide clock skew of less than 0.3 ns worst case. If not used, this pin must be set as LOW or HIGH on the board. It must not be left floating. Figure 1-7 shows the clock circuit used for the HCLK.
Table 1-1 * HiRel SX-A Clock Resources HiRel HiRel A54SX32A A54SX72A Hardwired Clocks (HCLK) Routed Clocks (CLKA, CLKB) Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 1 2 0 1 2 4
In addition, the HiRel A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. If QCLKs are not used as quadrant clocks, they will behave as regular I/Os. The CLKA, CLKB, and QCLK circuits for HiRel A54SX72A are shown in Figure 1-9. For more information, refer to the "Pin Description" section on page 1-31. For more information on how to use quadrant clocks in HiRel A54SX72A, refer to the Actel Global Clock Networks in Actel Antifuse Devices application note.
OE From Internal Logic To Internal Logic
Clock Network Constant Load Clock Network HCLKBUF
Figure 1-7 * HiRel SX-A Hardwired Load Clock Pad
The two routed clocks (CLKA and CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the HiRel SX-A device. CLKA and CLKB may be connected to sequential cells or to combinatorial logic. If the CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as LOW or HIGH on the board. They must not be left floating, except in HiRel A54SX72A, where they can be configured as regular I/Os. Figure 1-8 shows the CLKA and CLKB circuit used in HiRel A54SX32A.
CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI
Figure 1-9 *
From Internal Logic QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI
HiRel A54SX72A CLKA/CLKB/QCLK Pads
Other Architectural Features
Technology
The Actel HiRel SX-A family is implemented in a highvoltage twin-well CMOS using 0.25 m design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals. It also has a programmed ("on" state) resistance of 25 with a capacitance of 1.0 fF for low signal impedance.
Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI
Note: This does not include the clock pad for HiRel A54SX72A. Figure 1-8 * HiRel SX-A Routed Clock Pads
Performance
The combination of architectural features described above allows HiRel SX-A devices to operate with internal clock frequencies of 240 MHz, enabling very fast execution of complex logic functions. Thus, the HiRel SX-A family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs.
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In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into a HiRel SX-A device with dramatic improvements in cost and time-to-market. Using timingdriven place-and-route tools, designers can achieve highly deterministic device performance. With HiRel SX-A devices, designers do not need to use complicated performance-enhancing design techniques, such as redundant logic to reduce fanout on critical nets or the instantiation of macros in HDL code to achieve high performance.
system components and reduces overall design time. All unused I/Os are configured as tristate outputs by the Designer software. Each I/O module has an available power-up resistor of approximately 50 k that can configure the I/O to a known state during power-up. Just slightly before VCCA reaches 2.5 V, the resistors are disabled so the I/Os will behave normally. For more information about the power-up resistors, see the Actel application note Actel SX-A and RT54SX-S Devices in HotSwap and Cold-Sparing Applications. See Table 1-2 and Table 1-3 for more information on I/O features. HiRel SX-A inputs should be driven by high-speed pushpull devices with a low resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is not used, the high-resistance pull-up of the driver and the internal circuitry of the HiRel SX-A I/O, may create a voltage divider. This voltage divider could pull the input voltage below specification for some devices connected to the driver. A logic '1' may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 5 V to provide the logic '1' input, and VCCI is set to 3.3 V on the HiRel SX-A device, the input signal may be pulled down by the HiRel SX-A input.
I/O Modules
Each I/O on a HiRel SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards are allowed, and can be set on an individual basis. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-output-pad timing as fast as 4.1 ns. In most FPGAs, I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in HiRel SX-A FPGAs. Fast pin-to-pin timing ensures the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of
Table 1-2 * Function Two Input Buffer Threshold Selections Flexible Output Driver Output Buffer * * * * * * 5 V: PCI, TTL 3.3 V: PCI, LVTTL 5 V: PCI, TTL 3.3 V: PCI, LVTTL I/O Features
Description
Hot-Swap Capability (3.3 V PCI is not hot-swappable) I/O on an unpowered device does not sink current Can be used for cold sparing
Selectable on an individual I/O basis Individually selectable slew rate, high-slew or low-slew (the default is high slew rate). The slew is only affected on the falling edge of an output. No slew is changed on the rising edge of the output or any inputs. Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to power-up tristate) Enables deterministic power-up of device VCCA and VCCI can be powered in any order Table 1-3 * I/O Characteristics for All I/O Configurations Hot-Swappable TTL, LVTTL 3.3 V PCI 5 V PCI Yes No Yes Slew Rate Control Yes. Affects falling edge outputs only. No. High slew rate only. No. High slew rate only. Power-Up Resistor Pull Pull-up or pull-down Pull-up or pull-down Pull-up or pull-down
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Hot-Swapping
HiRel SX-A I/Os can be configured to be hot-swappable in compliance with the Compact PCI Specification. However, a 3.3 V PCI device is not hot-swappable. During power-up/down, all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down. After the HiRel SX-A device is plugged into an electrically active system, it will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip
Table 1-4 * Ramp Rate Units HiRel A54SX32A HiRel A54SX72A Power-Up Time at which I/Os Become Active 0.25 V/s s 10 10 0.025 V/s s 100 100 5 V/ms ms 0.46 0.41 2.5 V/ms ms 0.74 0.67 0.5 V/ms ms 2.8 2.6 0.25 V/ms ms 5.2 5.0 0.1 V/ms ms 12.1 12.1 0.025 V/ms ms 47.2 47.2
operating conditions are reached. Table 1-4 summarizes the VCCA voltage at which the I/Os behave according to the user's design for a HiRel SX-A device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5 V. Refer to the Actel application note Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications for more information on hot-swapping.
Power Requirements
The HiRel SX-A family supports 2.5 V/3.3 V/5 V mixedvoltage operation and is designed to tolerate 5 V inputs for all standards except 3.3 V PCI. In PCI mode, I/Os support 3.3 V or 5 V, and input tolerance depends on VCCI. Refer to Table 1-8 on page 1-11 and Table 1-10 on page 1-12 for more information. Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced due to the small number of antifuses in the path and the low-resistance properties of the antifuses. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture on the market.
Configuring Diagnostic Pins
The JTAG and probe pins (TDI, TCK, TMS, TDO, PRA, and PRB) are placed in the desired mode by selecting the appropriate check boxes in the Variation dialog window. This dialog window is accessible through the Design Setup Wizard under the Tools menu in the Actel Designer software. If JTAG I/Os (except TMS) are not programmed as dedicated JTAG I/Os, they can be used as regular I/Os.
TRST Pin
When the Reserve JTAG Test Reset box is checked, the TRST pin will become a Boundary Scan Reset pin. In this mode, the TRST pin functions as a dedicated, asynchronous, active low input to initialize or reset the BST circuit. An internal pull-up resistor will be enabled automatically on the TRST pin. The TRST pin will function as a user I/O when the Reserve JTAG Test Reset check box is cleared. The internal pull-up resistor will be disabled in this mode.
Boundary Scan Testing (BST)
All HiRel SX-A devices are IEEE 1149.1 compliant. HiRel SX-A devices offer superior diagnostic and testing capabilities by providing BST and probing capabilities. The BST function is controlled through the special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by one of two available modes: Dedicated and Flexible (Table 1-5). TMS cannot be employed as a user I/O in either mode.
Table 1-5 * Boundary Scan Pin Functionality Program Fuse Not Blown (Flexible Mode)
Dedicated Test Mode
When the Reserve JTAG box is checked in the Designer software, the HiRel SX-A device is placed in Dedicated Test mode, which configures the TDI, TCK, and TDO pins for BST or in-circuit verification with Silicon Explorer II. An internal pull-up resistor is automatically enabled on both the TMS and TDI pins. In Dedicated Test mode, TCK, TDI, and TDO are dedicated test pins and become unavailable for pin assignment in the Pin Editor. The TMS pin will function as specified in the IEEE 1149.1 (JTAG) specification.
Program Fuse Blown (Dedicated Test Mode)
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and BST pins. may be used as I/Os. No need for pull-up resistor for Use a pull-up resistor of 10 k TMS. on TMS.
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Flexible Mode
When the Reserve JTAG box is not selected, the HiRel SX-A device is placed in flexible mode, which allows the TDI, TCK, and TDO pins to function as user I/Os or BST pins. In this mode, the internal pull-up resistors on the TMS and TDI pins are disabled. An external 10 k pull-up resistor to VCCI is required on the TMS pin. The TDI, TCK, and TDO pins are transformed from user I/Os to BST pins when a rising edge on TCK is detected while TMS is at logical LOW. Once the BST pins are in test mode, they will remain in BST mode until the internal BST state machine reaches the "logic reset" state. At this point the BST pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set to logical HIGH. Synplify(R), ViewDraw(R), the Actel Designer software, ModelSim(R) HDL Simulator, WaveFormer LiteTM, and Actel Silicon Explorer II.
HiRel SX-A Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 1-10 illustrates the interconnection between Silicon Explorer II and the FPGA when performing in-circuit verification. The TRST pin is equipped with an internal pull-up resistor from the reset state during probing. It is recommended that TRST be left floating.
Development Tool Support
HiRel SX-A devices are fully supported by the Actel line of FPGA development tools, including the Actel Designer software and Actel Libero(R) Integrated Design Environment (IDE). Designer software, the Actel suite of FPGA development tools for PCs and Workstations, includes the ACTgen Macro Builder, timing-driven placeand-route, timing analysis tools, and fuse file generation. Libero IDE is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes necessary design data between tools. Libero IDE includes
Design Considerations
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, critical input signals through these pins are not available. In addition, do not program the Security Fuse, as this disables the Probe Circuit. Actel recommends that you use a series 70 termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, and PRB). The 70 termination is used to prevent data transmission corruption during probing and reading back the checksum.
16
Additional Channels 70 70 70 TDO 70 PRA 70 PRB HiRel SX-A FPGA
TDI Serial Connection Silicon Explorer II TCK TMS 70
Figure 1-10 * Probe Setup
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Related Documents
Application Notes
Global Clock Networks in Actel Antifuse Devices www.actel.com/documents/GlobalClk_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications www.actel.com/documents/HotSwapColdSparing_AN.pdf
Datasheets
SX-A Family FPGAs www.actel.com/documents/SXA_DS.pdf
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HiRel SX-A Family FPGAs
Detailed Specifications
2.5 V/3.3 V/5 V Operating Conditions
Table 1-6 * Symbol VCCI VCCA 2 VCCA VI VO 3 TSTG Notes: 1. Stresses beyond those listed under "Absolute maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. 2. The AC transient VCCA limit is for transients of less than 10 s duration and is not intended for repetitive use. Transients must not exceed 10 hours total duration over the lifetime of the part. Core voltage spikes from a single transient will not negatively impact the reliability of the device if, for this nonrepetitive event, the transient does not exceed 3.5 V at any time and the time that the transient exceeds 2.75 V does not exceed 10 s in duration. 3. VO max for 3.3 V PCI is VCCI + 0.5 V. For other I/O standards VO max is 6.0 V. Table 1-7 * Parameter Temperature Range* VCCA 2.5 V Power Supply Range VCCI 3.3 V Power Supply Range VCCI 5 V Power Supply Range Recommended Operating Conditions Military -55 to +125 2.25 to 2.75 3.0 to 3.6 4.5 to 5.5 Units C V V V Absolute Maximum Ratings1 Parameter DC Supply Voltage AC Supply Voltage DC Supply Voltage Input Voltage Output Voltage Storage Temperature Limits -0.3 to +6.0 -0.3 to +3.5 -0.3 to +3.0 -0.5 to +6.0 -0.5 to +VCCI +0.5 -65 to +150 Units V V V V V C
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.
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HiRel SX-A Family FPGAs
Table 1-8 *
3.3 V LVTTL and 5 V TTL Electrical Specifications Military
Symbol VOH VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VOL VIL1 VIH2 IIL/ IIH IOZ tR, tF CIO ICC IV Curve Notes:
3
Parameter (IOH = -1 mA) (IOH = -8 mA) (IOL = 1 mA) (IOL = 12 mA)
Min. 0.9VCCI 2.4
Max.
Units V V
VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND Tristate Output Leakage Current, VOUT = VCCI or GND Input Transition Time tR, tF I/O Capacitance Standby Current Can be derived from the IBIS model on the web
0.1VCCI 0.4 0.8 2.0 -20 -20 +20 +20 10 20 10 25
V V V V A A ns pF mA
1. For AC signals, the input signal may undershoot during transitions to -1.2 V for no longer than 11 ns. Current during the transition must not exceed 95 mA. 2. For AC signals, the input signal may overshoot during transitions to VCCI + 1.2 V for no longer than 11 ns. Current during the transition must not exceed 95 mA. 3. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html. 4. See the SX-A Family FPGAs datasheet for more information on commercial devices. Table 1-9 * Maximum Source and Sink Currents for All I/O Standards Max. Source Current I/O Standard 5 V TTL 3.3 V LVTTL 5 V PCI 3.3 V PCI Min. VOH 2.4 V 0.9VCCI 2.4 V 0.9VCCI 2.4 V 0.9VCCI I(typ) (mA) -139 -35 -43 -18 -139 -20 Max. Sink Current Max. VOL 0.4 V 0.1VCCI 0.4 V 0.1VCCI 0.55 V 0.1VCCI I(typ) (mA) 46 56 39 32 61.5 38
Note: This information is derived from the IBIS model and was taken under typical conditions. The numbers do not include derating for package resistance.
v2.0
1-11
HiRel SX-A Family FPGAs
5 V PCI Compliance for the HiRel SX-A Family
The HiRel SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 1-10 * DC Specifications, 5 V PCI Operation Symbol VCCA VCCI VIH VIL IIH IIL VOH VOL CIN CCLK Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and when used, AD[63:32], C/BE[7:4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage
1
Condition
Min. 2.25 4.5 2.0 -0.5
Max. 2.75 5.5 VCCI + 0.5 0.8 70 -70
Units V V V V A A V
1
Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage2
VIN = 2.7 VIN = 0.5 IOUT = -2 mA IOUT = 3 mA, 6 mA 2.4
0.55 10 5 12
V pF pF
Input Pin Capacitance3 CLK Pin Capacitance
Figure 1-11 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the HiRel SX-A family.
200.0 IOL MAX Spec 150.0 100.0 IOL MIN Spec Current (mA) 50.0 0.0 0 -50.0 -100.0 -150.0 -200.0 IOH Voltage Out (V)
Figure 1-11 * 5 V PCI Curve for HiRel SX-A Family
IOL
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
IOH MIN Spec IOH MAX Spec
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HiRel SX-A Family FPGAs
Table 1-11 * AC Specifications, 5 V PCI Operation Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT 1.4 3.1 < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 3.1 VOUT 2.2
3 1 1
Min. -44 (-44 + (VOUT - 1.4)/0.024
Max.
Units mA mA
1.4 VOUT < 2.4 1, 2
1, 3
EQ 1-1 on page 1-13 -142 95 VOUT/0.023 EQ 1-2 on page 1-13 206 -25 + (VIN + 1)/0.015 1 1 5 5 mA mA V/ns V/ns mA mA mA
2.2 > VOUT > 0.55 1 0.71 > VOUT > 0
1, 3 3
(Test Point) ICL slewR slewF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate
VOUT = 0.71
-5 < VIN -1 0.4 V - 2.4 V load 4 2.4 V - 0.4 V load
4
1. Refer to the V/I curves in Figure 1-11 on page 1-12. Switching current characteristics for REQ# and GNT# are permitted to be onehalf of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, or INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point, rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. EQ 1-1 and EQ 1-2 define these maxima. The equation defined maximum should be met by the design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (Figure 1-12) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components on the market for some time yet that have faster edge rates. Therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and they should ensure that signal integrity modeling accounts for this. Rise in slew rate does not apply to open drain outputs.
Pin 1/2" Maximum Output Buffer 1 k 10 pF 1 k VCC
Figure 1-12 * 5 V PCI Slew Load
IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1 V
EQ 1-1
IOL = 78.5 * VOUT * (4.4 - VOUT) for 0 V < VOUT < 0.71 V
EQ 1-2
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HiRel SX-A Family FPGAs
3.3 V PCI Compliance for the HiRel SX-A Family
The HiRel SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 1-12 * DC Specifications, 3.3 V PCI Operation Symbol VCCA VCCI VIH VIL IIPU IIL VOH VOL CIN CCLK Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floating network. Applications sensitive to static power utilization should ensure that the input buffer conducts minimal current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage Input Pull-Up Voltage1 Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance3 CLK Pin Capacitance 5
2
Condition
Min. 2.25 3.0 0.5VCCI -0.5 0.7VCCI
Max. 2.75 3.6 VCCI + 0.5 0.3VCCI
Units V V V V V
0 < VIN < VCCI IOUT = -500 A IOUT = 1500 A 0.9VCCI
20
A V
0.1VCCI 10 12
V pF pF
Figure 1-13 shows the 3.3 V PCI V-I curve and the minimum and maximum PCI drive characteristics of the HiRel SX-A family.
150.0 IOL MAX Spec 100.0 50.0 0.0 0 -50.0 -100.0 -150.0 Voltage Out (V)
Figure 1-13 * 3.3 V PCI V-I Curve for HiRel SX-A Family
IOL
Current (mA)
IOL MIN Spec
0.5 IOH MIN Spec
1
1.5
2
2.5
3
3.5
4
IOH
IOH MAX Spec
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HiRel SX-A Family FPGAs
Table 1-13 * AC Specifications, 3.3 V PCI Operation Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT 0.3VCCI
1
Min. -12VCCI -17.1 + (VCCI - VOUT)
Max.
Units mA mA
0.3VCCI VOUT < 0.9VCCI 1 0.7VCCI < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 0.7VCC
2 1 1, 2
EQ 1-3 -32VCCI 16VCCI 26.7VOUT EQ 1-4 38VCCI -25 + (VIN + 1)/0.015 25 + (VIN - VCCI - 1)/0.015 1 1 4 4 mA mA mA V/ns V/ns mA mA mA
VCCI > VOUT 0.6VCCI
0.6VCCI > VOUT > 0.1VCCI 1 0.18VCCI > VOUT > 0 (Test Point) ICL ICH slewR slewF Notes: Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18VCC -3 < VIN -1 VCCI + 4 > VIN VCCI + 1 0.2VCCI to 0.6VCCI load 0.6VCCI to 0.2VCCI
3 2 1, 2
load3
1. Refer to the V-I curves in Figure 1-13 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be onehalf of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, or INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. EQ 1-3 and EQ 1-4 define these maxima. The equation-defined maximum should be met by the design. To facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (Figure 1-14) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
Pin 1/2" Maximum Output Buffer 1 k 10 pF 1 k VCC
Figure 1-14 * 3.3 V PCI Slew Load
IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for VCCI > VOUT > 0.7VCCI
EQ 1-3
IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0 V < VOUT < 0.18VCC
EQ 1-4
v2.0
1-15
HiRel SX-A Family FPGAs
Junction Temperature (TJ)
The temperature variable selected in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated by dynamic power consumption usually produces a temperature hotter than the ambient temperature. EQ 1-5 can be used to calculate junction temperature. Junction Temperature = T + Ta
EQ 1-5
T = ja * P
EQ 1-6
where
P = Power
ja = Junction-to-ambient thermal resistance of package. ja values are given in Table 1-14.
where
Ta = Ambient temperature
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient characteristic is ja. In Table 1-14, the values of ja are given for two different air flow rates.
jc - 6.3 6.2 ja Still Air - 22 20 ja 300 ft/min - 14 10
T = Temperature gradient between junction (silicon) and ambient Table 1-14 * Sample Thermal Characteristics Package Type Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Pin Count 84 208 256
Units C/W C/W C/W
The maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a 256-pin CQFP package at commercial temperatures and in still air is given in EQ . 150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 4.0 W 20C/W ja (C/W)
EQ 1-7
For Device Power Calculator information, see the Software Tools section on the Actel website.
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HiRel SX-A Family FPGAs
HiRel SX-A Timing Model
Input Delays I/O Module tINYH = 1.0 ns tIRD1 = 0.5 ns tIRD2 = 0.7 ns Combinatorial Cell tPD = 1.2 ns tRD1 = 0.5 ns tRD4 = 1.2 ns tRD8 = 2.0 ns I/O Module tDHL = 4.5 ns Internal Delays Predicted Routing Delays Output Delays I/O Module tDHL = 4.5 ns
Register Cell
D
Q
tSUD = 1.0 ns tHD = 0.0 ns tRCKH = 3.9 ns (100% Load)
tRD1 = 0.5 ns
tENZL = 2.9 ns
Routed Clock
tRCO = 1.0 ns Register Cell
I/O Module tDHL = 4.5 ns
I/O Module tINYH = 1.0 ns tSUD = 1.0 ns tHD = 0.0 ns
D
Q
tRD1 = 0.5 ns
tENZL = 2.9 ns
Hardwired Clock
tHCKL = 2.2 ns
tRCO = 1.0 ns
Note: *Values shown for are HiRel A54SX72A-1, worst-case military conditions for VCCI = 3.0 V. Figure 1-15 * HiRel SX-A Timing Model
Hardwired Clock
External Setup = tINYH + tRD1 + tSUD - tHCKL = 1.0 + 0.5 + 1.0 - 2.2 = 0.3ns
EQ 1-8
Routed Clock
External Setup = tINYH + tRD1 + tSUD - tRCKH = 1.0 + 0.5 + 1.0 - 3.9 = -1.4 ns
EQ 1-10
Clock-to-Out (Pin-to-Pin) = tHCKL + tRCO + tRD1 + tDHL = 2.2 + 1.0 + 0.5 + 4.5 = 8.2 ns
EQ 1-9
Clock-to-Out (Pin-to-Pin) = tRCKH + tRCO + tRD1 + tDHL = 3.9 + 1.0 + 0.5 + 4.5 = 9.9 ns
EQ 1-11
v2.0
1-17
HiRel SX-A Family FPGAs
E D TRIBUFF PAD To AC Test Loads (shown below)
VCC D PAD VOL tDLH 50% 50% VOH 1.5 V tDHL GND 1.5 V E VCC PAD
VCC 50% 50% 1.5 V tENZL VOL 10% tENLZ GND E PAD GND
VCC 50% 50% VOH 1.5 V tENZH tENHZ GND 90%
Figure 1-16 * Output Buffer Delays
Load 1 (for propagation delays)
Load 2 (for enable delays) VCC R to VCC for tPZL R to GND for tPZH R = 1 k GND
Load 3 (for disable delays) VCC R to VCC for tPLZ R to GND for tPHZ R = 1 k From Output Under Test GND
From Output Under Test 35 pF
From Output Under Test 35 pF
5 pF
Figure 1-17 * AC Test Loads
PAD
INBUF
Y
S A B S, A, B VCC 50%
Y
3V PAD Y GND tINYH
Figure 1-18 * Input Buffer Delays
1.5 V
1.5 V VCC 50% tINYL
0V 50%
50% VCC tPD
GND 50% VCC 50%
Y GND Y tPD
50%
50% tPD
Figure 1-19 * C-Cell Delays
GND tPD
1 -1 8
v2.0
HiRel SX-A Family FPGAs
D CLK
PRESET CLR
Q
(Positive Edge Triggered) tHD D tSUD CLK tHPWL' tRPWL tRCO Q tCLR CLR tWASYN PRESET
Figure 1-20 * Cell Timing Characteristics
tHPWH' tRPWH
tHP
tPRESET
v2.0
1-19
HiRel SX-A Family FPGAs
Timing Characteristics
Timing characteristics for HiRel SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all HiRel SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after place-and-route of the user's design is complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to six percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 to 8.4 ns of delay. This additional delay is represented statistically in higherfanout (FO = 24) routing delays. See Table 1-16 on page 1-21 to Table 1-25 on page 1-30.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to place-and-route. Up to six percent of the nets in a design may be designated as critical, whereas 90 percent of the nets in a design are typical.
Timing Derating
HiRel SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case process characteristics. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
Table 1-15 * Temperature and Voltage Derating Factors Normalized to Worst-Case Military, TJ = 125C, VCCA = 2.25 V Junction Temperature (TJ) VCC 2.25 2.50 2.75 -55C 0.73 0.68 0.63 -40C 0.74 0.69 0.64 0C 0.80 0.75 0.70 25C 0.82 0.76 0.71 70C 0.90 0.84 0.78 85C 0.93 0.87 0.81 125C 1.00 0.94 0.87
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HiRel SX-A Family FPGAs
Table 1-16 * HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter C-Cell Propagation Delays tPD tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW tINYH tINYL tINYH tINYL tINYH tINYL tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Sequential Clock to Q Asynchronous Clear to Q Asynchronous Preset to Q Flip-Flop Data Input Setup Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Asynchronous Hold Time Clock Pulse Width Input Data Pad to Y HIGH 3.3 V PCI Input Data Pad to Y LOW 3.3 V PCI Input Data Pad to Y HIGH 3.3 V LVTTL Input Data Pad to Y LOW 3.3 V LVTTL Input Data Pad to Y HIGH 5 V PCI Input Data Pad to Y LOW 5 V PCI Input Data Pad to Y HIGH 5 V TTL Input Data Pad to Y LOW 5 V TTL FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 2.0 0.8 0.8 2.3 1.1 1.1 1.3 2.2 1.3 0.5 0.7 0.9 1.2 2 2.9 0.8 0.0 1.7 0.7 0.7 2.3 0.9 1.0 2.7 1.3 1.2 1.5 2.6 1.5 0.6 0.8 1 1.3 2.4 3.5 0.9 0.7 0.8 1.0 0.0 2.0 0.9 0.9 1.1 0.8 0.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Predicted Routing
1
'Std' Speed Min. Max. 1.4 0.1 0.2 0.6 0.8 1 1.3 2.4 3.5 Units ns ns ns ns ns ns ns ns ns
Description Internal Array Module Delays2 FO = 1 Routing Delay, DirectConnect FO = 1 Routing Delay, FastConnect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
Min.
Max. 1.2 0.1 0.2 0.5 0.7 0.9 1.2 2 2.9
Input Module Propagation Delays
Input Module Predicted Routing Delays2
v2.0
1-21
HiRel SX-A Family FPGAs
Table 1-17 * HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Dedicated (hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (pad to R-Cell input) Input High to Low (pad to R-Cell input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.0 250 2.0 2.0 1.3 4.6 217 2.5 2.3 2.3 2.3 1.5 3.0 2.7 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Low to High (pad to R-Cell input, light load) Input High to Low (pad to R-Cell input, light load) Input Low to High (pad to R-Cell input, 50% load) Input High to Low (pad to R-Cell input, 50% load) Input Low to High (pad to R-Cell input, 100% load) Input High to Low (pad to R-Cell input, 100% load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (light load) Maximum Skew (50% load) Maximum Skew (100% load) 2.0 2.0 2.5 2.7 2.7 3.3 2.9 3.5 3.0 3.7 3.2 2.3 2.3 2.9 3.2 3.2 3.8 3.4 4.2 3.5 4.3 3.8 ns ns ns ns ns ns ns ns ns ns ns
1 -2 2
v2.0
HiRel SX-A Family FPGAs
Table 1-18 * HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 4.75 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Dedicated (hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (pad to R-Cell input) Input High to Low (pad to R-Cell input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.0 250 2.0 2.0 1.4 4.6 217 2.5 2.3 2.3 2.3 1.7 3.0 2.7 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Low to High (pad to R-Cell input, light load) Input High to Low (pad to R-Cell input, light load) Input Low to High (pad to R-Cell input, 50% load) Input High to Low (pad to R-Cell input, 50% load) Input Low to High (pad to R-Cell input, 100% load) Input High to Low (pad to R-Cell input, 100% load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (light load) Maximum Skew (50% load) Maximum Skew (100% load) 2.0 2.0 2.5 2.7 2.8 3.4 2.9 3.6 3.1 3.8 3.3 2.3 2.3 3.0 3.2 3.3 3.9 3.4 4.3 3.6 4.4 3.9 ns ns ns ns ns ns ns ns ns ns ns
v2.0
1-23
HiRel SX-A Family FPGAs
Table 1-19 * A54SX32A Timing Characteristics (Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C) -1 Speed Parameter Description Timing1 3.1 3.6 2.0 3.1 3.8 2.8 0.02 0.05 3.6 4.2 2.3 3.6 4.5 3.3 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF Min. Max. Std. Speed Min. Max. Units
3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading. Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low 4.3 3.6 3.9 4.3 4.2 3.6 0.02 0.05 5.1 4.2 4.6 5.1 4.9 4.2 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF
1 -2 4
v2.0
HiRel SX-A Family FPGAs
Table 1-20 * A54SX32A Timing Characteristics (Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 125C) -1 Speed Parameter Description Timing1 3.6 3.7 2.0 3.6 4.1 3.7 0.02 0.05 4.2 4.4 2.3 4.2 4.8 4.4 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF Min. Max. Std. Speed Min. Max. Units
5.0 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5.0 V LVTTL Output Module Timing3 tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading. Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low 3.2 3.4 3.9 3.2 5.1 3.4 0.02 0.05 3.8 4.0 4.6 3.8 6.0 4.0 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF
v2.0
1-25
HiRel SX-A Family FPGAs
Table 1-21 * HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter C-Cell Propagation Delays tPD tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW tINYH tINYL tINYH tINYL tINYH tINYL tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Sequential Clock to Q Asynchronous Clear to Q Asynchronous Preset to Q Flip-Flop Data Input Setup Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Asynchronous Hold Time Clock Pulse Width Input Data Pad to Y HIGH 3.3 V PCI Input Data Pad to Y LOW 3.3 V PCI Input Data Pad to Y HIGH 3.3 V LVTTL Input Data Pad to Y LOW 3.3 V LVTTL Input Data Pad to Y HIGH 5 V PCI Input Data Pad to Y LOW 5 V PCI Input Data Pad to Y HIGH 5 V TTL Input Data Pad to Y LOW 5 V TTL FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 2.2 0.9 1.0 1.0 1.4 0.8 1.1 1.1 1.1 0.5 0.7 0.9 1.2 2 2.9 1.0 0.0 1.9 0.8 0.8 2.6 1.1 1.1 1.2 1.7 1.0 1.2 1.2 1.3 0.6 0.8 1 1.3 2.4 3.5 1.0 0.8 0.9 1.1 0.0 2.2 1.0 1.0 1.2 0.9 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Predicted Routing
1
'Std' Speed Min. Max. 1.4 0.1 0.2 0.6 0.8 1 1.3 2.4 3.5 Units ns ns ns ns ns ns ns ns ns
Description Internal Array Module Delays2 FO = 1 Routing Delay, DirectConnect FO = 1 Routing Delay, FastConnect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
Min.
Max. 1.2 0.1 0.2 0.5 0.7 0.9 1.2 2 2.9
Input Module Propagation Delays
Input Module Predicted Routing Delays2
1 -2 6
v2.0
HiRel SX-A Family FPGAs
Table 1-22 * HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tQCKH tQCHKL tQCKH tQCHKL tQCKH tQCHKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Description Input Low to High (pad to R-Cell input) Input High to Low (pad to R-Cell input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency Input Low to High (pad to R-Cell input, light load) Input High to Low (pad to R-Cell input, light load) Input Low to High (pad to R-Cell input, 50% load) Input High to Low (pad to R-Cell input, 50% load) Input Low to High (pad to R-Cell input, 100% load) Input High to Low (pad to R-Cell input, 100% load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (light load) Maximum Skew (50% load) Maximum Skew (100% load) Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.2 2.2 1.5 1.7 1.9 2.2 2.2 3.3 3.4 3.5 2.0 1.8 2.3 2.1 2.6 2.3 2.6 2.6 1.8 2 2.2 4.4 227 3.3 3.8 3.6 3.9 3.9 4.2 2.6 2.6 3.9 3.9 4.1 2.3 2.1 2.7 2.4 3.0 2.7 2.2 2.2 2 5.2 192 3.9 4.5 4.2 4.6 4.6 4.9 Min. Max. 2.4 2.2 2.6 2.6 2.4 Dedicated (hardwired) Array Clock Network 2.8 2.6 ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 'Std' Speed Min. Max. Units
Routed Array Clock Networks
Quadrant Array Clock Networks
v2.0
1-27
HiRel SX-A Family FPGAs
Table 1-23 * HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, VCCA = 2.25 V, VCCI = 4.75 V, TJ = 125C '-1' Speed Parameter tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tQCKH tQCHKL tQCKH tQCHKL tQCKH tQCHKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Description Input Low to High (pad to R-Cell input) Input High to Low (pad to R-Cell input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency Input Low to High (pad to R-Cell input, light load) Input High to Low (pad to R-Cell input, light load) Input Low to High (pad to R-Cell input, 50% load) Input High to Low (pad to R-Cell input, 50% load) Input Low to High (pad to R-Cell input, 100% load) Input High to Low (pad to R-Cell input, 100% load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (light load) Maximum Skew (50% load) Maximum Skew (100% load) Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.2 2.2 1.3 1.5 1.7 2.2 2.2 3.3 3.4 3.6 1.9 1.7 2.2 2.0 2.5 2.3 2.6 2.6 1.5 1.8 2.0 4.4 227 3.5 3.8 3.7 4.1 3.9 4.3 2.6 2.6 3.9 4.0 4.2 2.2 2.0 2.6 2.3 2.9 2.6 2.2 2.2 2.1 5.2 192 4.1 4.5 4.4 4.8 4.6 5.1 Min. Max. 2.4 2.2 2.6 2.6 2.4 Dedicated (hardwired) Array Clock Network 2.8 2.6 ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 'Std' Speed Min. Max. Units
Routed Array Clock Networks
Quadrant Array Clock Networks
1 -2 8
v2.0
HiRel SX-A Family FPGAs
Table 1-24 * A54SX72A Timing Characteristics (Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125C) -1 Speed Parameter Description Timing1 3.5 3.8 1.9 3.5 3.2 3.8 0.02 0.05 4.1 4.5 2.2 4.1 3.8 4.5 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF Min. Max. Std. Speed Min. Max. Units
3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading. Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low 5.1 4.5 2.9 5.1 3.7 4.5 0.02 0.05 5.9 5.3 3.4 5.9 4.4 5.3 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF
v2.0
1-29
HiRel SX-A Family FPGAs
Table 1-25 * A54SX72A Timing Characteristics (Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 125C) -1 Speed Parameter Description Timing1 4.2 4.3 1.7 4.2 3.9 4.3 0.02 0.05 4.9 5.0 2.0 4.9 4.6 5.0 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF Min. Max. Std. Speed Min. Max. Units
5.0 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5.0 V LVTTL Output Module Timing3 tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading. Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low 3.9 4.2 2.7 3.9 4.7 4.2 0.02 0.05 4.6 4.9 3.2 4.6 5.6 4.9 0.04 0.05 ns ns ns ns ns ns ns/pF ns/pF
1 -3 0
v2.0
HiRel SX-A Family FPGAs
Pin Description
CLKA/B Clock A/B I/O Input/Output
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. The clock input is buffered prior to clocking the R-cells. If unused, these pins must be fixed LOW or HIGH on the board. They must not be left floating (for HiRel A54SX72A, these clocks can be configured as user I/O).
QCLKA/B/C/D, I/O Quadrant Clock A/B/C/D, I/O
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. Unused I/O pins are automatically tristated by the Designer software.
NC No Connection
These four pins are the clock inputs for the quadrant clock distribution networks and only exist on HiRel A54SX72A. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. If not used as a clock, each input will behave as a regular I/O.
GND Ground
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or left floating with no effect on the operation of the device.
PRA/B, I/O1 Probe A/B
LOW supply voltage.
HCLK Dedicated (hardwired) Array Clock
The Probe pin is used to put out data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the other Probe pin to allow real-time diagnostic output of any signal path within the device. A Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be disabled permanently to protect programmed design confidentiality.
TCK, I/O1 Test Clock
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. This input is wired directly to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must set LOW or HIGH on the board. It must not be left floating.
Test clock input for diagnostic probe and device programming. In Flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 1-5 on page 1-7). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
1. 70 series termination should be placed on the board to enable probing capability.
v2.0
1-31
HiRel SX-A Family FPGAs TDI, I/O1 Test Data Input TRST, I/O Boundary Scan Reset Pin
Serial input for boundary scan testing and diagnostic probe. In Flexible mode, TDI is active when the TMS pin is set LOW (Table 1-5 on page 1-7). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDO, I/O1 Test Data Output
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active low input that may be used to asynchronously initialize or reset the boundary scan circuitry. The TRST pin is equipped with an internal pullup resistor. This pin functions as an I/O when the Reserve JTAG Test Reset Pin check box is cleared in the Actel Designer software.
VCCI Supply Voltage
Serial output for boundary scan testing. In Flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 1-5 on page 1-7). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer is being used, TDO acts as an output when the checksum command is run. It will return to a user I/O when the checksum is complete.
TMS1 Test Mode Select
Supply voltage for I/Os. See Table 1-7 on page 1-10. All VCCI power pins in the device should be connected.
VCCA Supply Voltage
Supply voltage for array. See Table 1-7 on page 1-10. All VCCA power pins in the device should be connected.
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, and TRST). In Flexible mode, when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-5 on page 1-7). Once the boundary scan pins are in test mode, they remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins are released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specification.
1 -3 2
v2.0
HiRel SX-A Family FPGAs
Package Pin Assignments
84-Pin CQFP
Pin #1 Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
84-Pin CQFP
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Figure 2-1 *
208-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html.
v2.0
2-1
HiRel SX-A Family FPGAs
84-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 HiRel A54SX32A Function I/O I/O TMS I/O VCCI GND I/O I/O I/O I/O TRST I/O I/O I/O VCCA GND I/O VCCA I/O I/O I/O I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O PRB, I/O HCLK I/O I/O
84-Pin CQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 HiRel A54SX32A Function VCCA GND I/O TDO, I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCA GND I/O I/O I/O I/O I/O I/O VCCI GND I/O
84-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 HiRel A54SX32A Function I/O CLKA CLKB PRA, I/O I/O I/O I/O GND VCCA I/O I/O TCK, I/O TDI, I/O I/O
2 -2
v2.0
HiRel SX-A Family FPGAs
208-Pin CQFP
208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157
Pin #1 Index
1 2 3 4 5 6 7 8
156 155 154 153 152 151 150 149
208-Pin CQFP
44 45 46 47 48 49 50 51 52 113 112 111 110 109 108 107 106 105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
Figure 2-2 *
208-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html.
v2.0
2-3
HiRel SX-A Family FPGAs
208-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 HiRel A54SX32A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
208-Pin CQFP HiRel A54SX32A Function I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA Pin Number 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
208-Pin CQFP HiRel A54SX32A Function I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O PRB, I/O GND VCCA GND NC I/O HCLK VCCI QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O
2 -4
v2.0
HiRel SX-A Family FPGAs
208-Pin CQFP Pin Number 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 HiRel A54SX32A Function I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI HiRel A54SX72A Function I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI Pin Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
208-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND HiRel A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD I/O CLKA CLKB NC GND VCCA GND Pin Number 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin CQFP HiRel A54SX32A Function PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O HiRel A54SX72A Function PRA, I/O VCCI I/O I/O QCLKC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O
v2.0
2-5
HiRel SX-A Family FPGAs
256-Pin CQFP
256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193
Pin #1 Index
1 2 3 4 5 6 7 8
192 191 190 189 188 187 186 185
256-Pin CQFP
56 57 58 59 60 61 62 63 64 137 136 135 134 133 132 131 130 129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
Figure 2-3 *
256-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html.
2 -6
v2.0
HiRel SX-A Family FPGAs
256-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 HiRel A54SX32A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST, I/O I/O I/O I/O HiRel A54SX72A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST, I/O I/O VCCA GND Pin Number 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O Pin Number 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O HiRel A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA PRB, I/O GND VCCI GND VCCA I/O HCLK I/O QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O
v2.0
2-7
HiRel SX-A Family FPGAs
256-Pin CQFP Pin Number 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O Pin Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O Pin Number 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND HiRel A54SX72A Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD CLKA CLKB VCCI GND
2 -8
v2.0
HiRel SX-A Family FPGAs
256-Pin CQFP Pin Number 223 224 225 226 227 228 229 230 231 232 233 234 HiRel A54SX32A Function NC GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O HiRel A54SX72A Function NC GND PRA, I/O I/O I/O VCCA I/O I/O QCLKC I/O I/O I/O Pin Number 235 236 237 238 239 240 241 242 243 244 245
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O HiRel A54SX72A Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O Pin Number 246 247 248 249 250 251 252 253 254 255 256
256-Pin CQFP HiRel A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O HiRel A54SX72A Function I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O
v2.0
2-9
HiRel SX-A Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Advanced v1.2 (December 2002) Changes in current version--v2.0 The 84-pin CQFP package information was added to the datasheet. The Product Plan table was deleted because all of the devices are production devices. Table 1-6 * Absolute Maximum Ratings1 was updated to include VCCA AC supply voltage information. In addition, two notes were added to the table. Notes 1 and 2 were added to Table 1-8 * 3.3 V LVTTL and 5 V TTL Electrical Specifications. The "HiRel SX-A Timing Model" was updated. The "Hardwired Clock" and "Routed Clock" equations were updated. All of the Timing Characteristic tables were updated because to include the fully characterized data. Advanced v1.1 Table 1-8 * 3.3 V LVTTL and 5 V TTL Electrical Specifications was updated. Table 1-12 * DC Specifications, 3.3 V PCI Operation was updated. Preliminary v1.0 The "Ordering Information" section was updated. Figure 1-1 * HiRel SX-A Family Interconnect Elements was updated. The "Clock Resources" section was updated. The "I/O Modules" section was updated. Table 1-2 * I/O Features was updated. The "Hot-Swapping" section was updated. Table 1-3 * I/O Characteristics for All I/O Configurations is new. Table 1-4 * Power-Up Time at which I/Os Become Active is new. The "Power Requirements" section was updated. The "Design Considerations" section was updated. Figure 1-10 * Probe Setup was updated. Table 1-6 * Absolute Maximum Ratings1 was updated. Table 1-7 * Recommended Operating Conditions was updated. Table 1-9 * Maximum Source and Sink Currents for All I/O Standards is new. Figure 1-15 * HiRel SX-A Timing Model was updated. The "Pin Description" section was updated. Page N/A N/A 1-10 1-11 1-17 1-17 N/A 1-11 1-14 ii 1-1 1-5 1-6 1-6 1-7 1-6 1-7 1-7 1-8 1-8 1-10 1-10 1-11 1-17 1-31
v2.0
3-1
HiRel SX-A Family FPGAs
Previous version Advanced v0.1
Changes in current version--v2.0 (Continued) The "Clock Resources" section was updated. The "I/O Modules" section was updated. The "Hot-Swapping" section was updated. The "Power Requirements" section was updated. The "Boundary Scan Testing (BST)" section has been updated. The "Configuring Diagnostic Pins" section has been updated. The "TRST Pin" section has been updated. The "Dedicated Test Mode" section has been updated. The "Development Tool Support" section has been updated. The "HiRel SX-A Probe Circuit Control Pins" section has been updated. The "Pin Description" section was updated. The "Package Characteristics and Mechanical Drawings" section has been eliminated from the datasheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site.
Page 1-5 1-6 1-7 1-7 1-7 1-7 1-7 1-7 1-8 1-8 1-31
3 -2
v2.0
HiRel SX-A Family FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR)
The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export can include a release or disclosure to a foreign national inside or outside the United States.
v2.0
3-3
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600
Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley, Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540
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5172148-4/11.06

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